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Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT

Abstract : This work demonstrates an ultra-low power, software-defined wireless transceiver designed for IoT applications using an open-source 32-bit RISC-V core. The key driver behind this success is an optimized hardware/software partitioning of the receiver's digital signal processing operators. We benchmarked our architecture on an algorithm for the detection of FSK-modulated frames using a RISC-V compatible core and ARM Cortex-M series processors. We use only standard compilation tools and no assembly-level optimizations. Our results show that Bluetooth LE frames can be detected with an estimated peak core power consumption of 1.6 mW on a 28 nm FDSOI technology, and falling to less than 0.6 mW (on average) during symbol demodulation. This is achieved at nominal voltage. Compared to state of the art, our work offers a power efficient alternative to the design of dedicated baseband processors for ultra-low power software-defined radios with a low software complexity.
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https://hal-cea.archives-ouvertes.fr/cea-01936120
Contributor : Carolynn Bernier <>
Submitted on : Tuesday, November 27, 2018 - 11:38:45 AM
Last modification on : Thursday, June 11, 2020 - 5:04:07 PM
Long-term archiving on: : Thursday, February 28, 2019 - 2:22:17 PM

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Hela Amor, Carolynn Bernier. Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT. Design, Automation and Test in Europe (DATE), Mar 2019, Florence, Italy. ⟨cea-01936120⟩

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