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Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Abstract : The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs. height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11 nm. (C) 2016 Elsevier Ltd. All rights reserved.
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https://hal-cea.archives-ouvertes.fr/cea-01851576
Contributor : Jérôme Planès Connect in order to contact the contributor
Submitted on : Monday, July 30, 2018 - 2:31:54 PM
Last modification on : Tuesday, May 11, 2021 - 11:36:11 AM

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Johan Pelloux-Prayer, Mikael Casse, Francois Triozon, Sylvain Barraud, Yann-Michel Niquet, et al.. Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model. Solid-State Electronics, Elsevier, 2016, 125, pp.175-181. ⟨10.1016/j.sse.2016.09.002⟩. ⟨cea-01851576⟩

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