Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model - Archive ouverte HAL Access content directly
Journal Articles Solid-State Electronics Year : 2016

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

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Abstract

The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs. height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11 nm. (C) 2016 Elsevier Ltd. All rights reserved.
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Dates and versions

cea-01851576 , version 1 (30-07-2018)

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Johan Pelloux-Prayer, Mikael Casse, Francois Triozon, Sylvain Barraud, Yann-Michel Niquet, et al.. Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model. Solid-State Electronics, 2016, 125, pp.175-181. ⟨10.1016/j.sse.2016.09.002⟩. ⟨cea-01851576⟩
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