A fast and accurate methodology for power estimation and reduction of programmable architectures

E. Piriou; R. David; F. Rahim; S. Rahim

doi:10.7873/DATE.2013.220

Conference papers

A fast and accurate methodology for power estimation and reduction of programmable architectures

E. Piriou ¹ R. David ¹ F. Rahim ² S. Rahim ²

1 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST

2 Atrenta Inc.

Abstract : We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. We demonstrate a 19% improvement for a standard RISC processor.

Keywords : Register files Register transfer level RISC processors Programmable architectures Power Optimization Power estimations Instruction-level Design space exploration

Document type :

Conference papers

Domain :

Computer Science [cs]

Engineering Sciences [physics]

Complete list of metadatas

https://hal-cea.archives-ouvertes.fr/cea-01844718
Contributor : Léna Le Roy <>
Submitted on : Thursday, July 19, 2018 - 3:58:08 PM
Last modification on : Monday, February 10, 2020 - 6:14:16 PM

A fast and accurate methodology for power estimation and reduction of programmable architectures

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A fast and accurate methodology for power estimation and reduction of programmable architectures

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