A fast and accurate methodology for power estimation and reduction of programmable architectures

Abstract : We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. We demonstrate a 19% improvement for a standard RISC processor.
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-01844718
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Submitted on : Thursday, July 19, 2018 - 3:58:08 PM
Last modification on : Wednesday, January 23, 2019 - 2:39:33 PM

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E. Piriou, R. David, F. Rahim, S. Rahim. A fast and accurate methodology for power estimation and reduction of programmable architectures. 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013;, Mar 2013, Grenoble, France. pp.1054-1055, ⟨10.7873/DATE.2013.220⟩. ⟨cea-01844718⟩

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