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Conference papers
A new parallel SystemC kernel leveraging manycore architectures
Abstract : The complexity of system-level modeling is continuously increasing. Electronic System Level (ESL) design requires fast simulation techniques to control future SoC development cost and time-to-market. However, SystemC simulations are sequential and then limited by single-thread performance. In this paper, we present a new parallel SystemC kernel that efficiently leverages the multiple cores of a host machine, reaching high simulation performance without relaxing accuracy. It supports atomic parallel evaluation of SystemC processes and repeatable execution for HW/SW debugging. This new kernel is fully compliant with existing standards and easy to integrate in any existing SystemC model. Evaluations show a maximum acceleration of 34× compared to Accellera SystemC on a 64-core AMD Opteron machine.
https://hal-cea.archives-ouvertes.fr/cea-01843186
Contributor : Léna Le Roy <>
Submitted on : Wednesday, July 18, 2018 - 3:55:59 PM
Last modification on : Monday, February 10, 2020 - 6:14:16 PM
Contributor : Léna Le Roy <>
Submitted on : Wednesday, July 18, 2018 - 3:55:59 PM
Last modification on : Monday, February 10, 2020 - 6:14:16 PM