Skip to Main content Skip to Navigation
Conference papers

A new parallel SystemC kernel leveraging manycore architectures

Abstract : The complexity of system-level modeling is continuously increasing. Electronic System Level (ESL) design requires fast simulation techniques to control future SoC development cost and time-to-market. However, SystemC simulations are sequential and then limited by single-thread performance. In this paper, we present a new parallel SystemC kernel that efficiently leverages the multiple cores of a host machine, reaching high simulation performance without relaxing accuracy. It supports atomic parallel evaluation of SystemC processes and repeatable execution for HW/SW debugging. This new kernel is fully compliant with existing standards and easy to integrate in any existing SystemC model. Evaluations show a maximum acceleration of 34× compared to Accellera SystemC on a 64-core AMD Opteron machine.
Document type :
Conference papers
Complete list of metadata
Contributor : Léna Le Roy Connect in order to contact the contributor
Submitted on : Wednesday, July 18, 2018 - 3:55:59 PM
Last modification on : Thursday, February 17, 2022 - 10:08:06 AM


  • HAL Id : cea-01843186, version 1


N. Ventroux, T. Sassolas. A new parallel SystemC kernel leveraging manycore architectures. 19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Mar 2016, Dresden, Germany. pp.487-492. ⟨cea-01843186⟩



Record views