A formal evaluation of mean-time access latencies for interleaved on-chip shared banked-memory in manycores - Archive ouverte HAL Access content directly
Conference Papers Year : 2013

A formal evaluation of mean-time access latencies for interleaved on-chip shared banked-memory in manycores

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Abstract

In many core architectures, clusters with shared memory banks offer a simple and efficient way (high throughput, low latency) to share and communicate data between close cores. Several recent embedded architectures are using such a design e.g. the MPPA chip from Kalray. Nonetheless, especially in the embedded world, as power consumption is an important preoccupation, shared memory is implemented as a set of single-port memory banks managed by a dedicated controller. As a consequence, some serialization is mandatory for concurrent accesses to banks. This means that memory access-time delays can occur on a regular basis, as each cluster is a multicore system by itself. This paper evaluates on a theoretical basis what kind of tradeoff is made by using such a design with regards to memory access-times and real-time performance: it evaluates the mean access-time with the default configuration of the MPPA chip on a probabilistic formalism, and gives a simplified expression of it. It also gives some typical values for use cases, and discuss the relevance of this design and its limitations with regards to the use of dataflow (CSDF) models of computation.
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Dates and versions

cea-01838149 , version 1 (13-07-2018)

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S. Louise. A formal evaluation of mean-time access latencies for interleaved on-chip shared banked-memory in manycores. 2013 IEEE 7th International Symposium on Embedded Multicore Socs, Sep 2013, Tokyo, Japan. pp.19-24, ⟨10.1109/MCSoC.2013.16⟩. ⟨cea-01838149⟩

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