Shadow-scan design with low latency overhead and in-situ slack-time monitoring

S. Sarrazin 1 S. Evain 1 I. Miro-Panades 2 A. Valentian 2 S. Pajaniradja 1 L.A. de Barros Naviner 3 V. Gherman 1
1 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST
2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
3 Télécom ParisTech
Abstract : Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided.
Keywords : Design for testability latency overhead Online monitoring Scan designs shadow-scan timing violations Scanning
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-01838144
Contributor : Léna Le Roy <>
Submitted on : Friday, July 13, 2018 - 10:28:59 AM
Last modification on : Friday, December 20, 2019 - 1:36:37 AM

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CEA | DRT | LETI | LIST | CEA-GRE | INSTITUT-TELECOM | PARISTECH

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S. Sarrazin, S. Evain, I. Miro-Panades, A. Valentian, S. Pajaniradja, et al.. Shadow-scan design with low latency overhead and in-situ slack-time monitoring. 2014 19th IEEE European Test Symposium (ETS), May 2014, Paderborn, Germany. ⟨10.1109/ETS.2014.6847801⟩. ⟨cea-01838144⟩

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