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Conference Papers Year : 2015

Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor

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Abstract

Power efficiency is a tremendous challenge for high performance embedded systems under energy constraints. Fine grain Dynamic Voltage and Frequency Scaling approaches are usually implemented in order to meet these conflicting objectives. Moreover, these techniques can be improved if local and on-the-fly monitoring of the dynamic variations is performed. A low-cost onchip general purpose sensor associated with an appropriate data fusion technique has been recently developed in order to monitor local temperature and voltage conditions. However, reliability has become a major concern as the technology scales below 40nm. The aging variation is not anymore negligible and must be taken into account during the monitor design and operation. This paper revisits such a sensor under both BTI and HCI aging effects in 28nm STMicroelectronics technology. A simple recalibration method is also proposed to mitigate the aging effects on the VT estimation.
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Dates and versions

cea-01838141 , version 1 (13-07-2018)

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Cite

M. Altieri, S. Lesecq, D. Puschini, O. Heron, E. Beigne, et al.. Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor. 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep 2015, Salvador, Brazil. pp.111-117, ⟨10.1109/PATMOS.2015.7347595⟩. ⟨cea-01838141⟩
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