FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs
Résumé
The number of cores is increasing in processor designs. By having the same duplicated core increases dark silicon and reduces the scalability of multicore/many-core designs. Asymmetric distribution of ISA specialized units (i.e. FPU and SIMD units) in multicore designs can bring new opportunities for performance gain, area and energy savings. Basically, the task placement is driven by the requirement of the specialized resources. To improve task-mapping flexibility, solutions such as code-versioning or binary translation allow the OS to place any task on any type of core. However, a specialized execution unit such as FPU is able to speedup some part up to 1000x compared to the same function emulated with Integer execution units. On one hand, mapping all tasks on the core with the FPU creates a bottleneck, and on the other hand, mapping a high FPU-usage application on a core without FPU drastically degrades the performance. To allow a smarter placement, the OS needs to know the potential advantage of using the FPU for each thread. In this paper, we demonstrate that only using the trivial percentage utilization is not enough to have an accurate estimation. We propose a finer grain solution to estimate the speedup of the FPU at runtime. The average of the absolute error is 14 %, which is 4.8 times better than the trivial coarse estimation. Then we characterize the different types of FPU-usage through a set of common benchmarks and show the variability of the utilization during the execution.