A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC

Abstract : In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy gains due to local adaptability. Compared to a worst case approach, our proposal also allows a frequency boosting around 25% for a total area overhead of 10% including local frequency/voltage actuators, sensors and digital controller.
Document type :
Conference papers
Complete list of metadatas

https://hal-cea.archives-ouvertes.fr/cea-01837015
Contributor : Léna Le Roy <>
Submitted on : Thursday, July 12, 2018 - 3:52:20 PM
Last modification on : Monday, July 1, 2019 - 4:20:04 PM

Identifiers

Collections

CEA | DRT | LETI | LIST | CEA-GRE

Citation

E. Beigne, I. Miro-Panades, Y. Thonnart, L. Alacoque, Pascal Vivet, et al.. A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. 2013 Proceedings of the ESSCIRC (ESSCIRC), Sep 2013, Bucharest, Romania. pp.57-60, ⟨10.1109/ESSCIRC.2013.6649071⟩. ⟨cea-01837015⟩

Share

Metrics

Record views

41