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A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC

E. Beigne 1 I. Miro-Panades 1 Y. Thonnart 1 L. Alacoque 1 Pascal Vivet 1 S. Lesecq 1 D. Puschini 1 F. Thabet 2 B. Tain 2 K. Benchehida 2 Sylvain Engels 3 R. Wilson 3 D. Fuin 3
1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST
3 ST-CROLLES - STMicroelectronics [Crolles]
Abstract : In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy gains due to local adaptability. Compared to a worst case approach, our proposal also allows a frequency boosting around 25% for a total area overhead of 10% including local frequency/voltage actuators, sensors and digital controller.
Keywords : Local frequency Multi-processor SoC Processing elements Voltage-frequency islands Energy efficiency Microprocessor chips Frequency-scaling Digital controllers Area overhead Adaptive voltage
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-01837015
Contributor : Léna Le Roy Connect in order to contact the contributor
Submitted on : Thursday, July 12, 2018 - 3:52:20 PM
Last modification on : Friday, June 25, 2021 - 9:48:10 AM

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E. Beigne, I. Miro-Panades, Y. Thonnart, L. Alacoque, Pascal Vivet, et al.. A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. 2013 Proceedings of the ESSCIRC (ESSCIRC), Sep 2013, Bucharest, Romania. pp.57-60, ⟨10.1109/ESSCIRC.2013.6649071⟩. ⟨cea-01837015⟩

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