Skip to Main content Skip to Navigation
Conference papers

Reducing power with activity trigger analysis

Abstract : In this paper we propose and implement a methodology for power reduction in digital circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating. We introduce a new class of coarse grained local clock gating conditions and develop a method for detecting such conditions and formally proving their correctness. The detection of these conditions relies on architecture characterization and statistical analysis of simulation, all done at the RTL. Formal verification is performed on an abstract circuit model. We demonstrate a significant power reduction from 33 to 40% of total power on a clusterized circuit design for video processing.
Document type :
Conference papers
Complete list of metadatas

https://hal-cea.archives-ouvertes.fr/cea-01836860
Contributor : Léna Le Roy <>
Submitted on : Thursday, July 12, 2018 - 3:05:28 PM
Last modification on : Friday, July 17, 2020 - 11:48:06 AM

Links full text

Identifiers

Collections

Citation

J. Lanik, J. Legriel, E. Piriou, E. Viaud, F. Rahim, et al.. Reducing power with activity trigger analysis. 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), Sep 2015, Austin, United States. pp.169-178, ⟨10.1109/MEMCOD.2015.7340484⟩. ⟨cea-01836860⟩

Share

Metrics

Record views

321