Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores

Abstract : Many-core architectures are promising hardware to design hard real-time systems as they are based on simpler and thus more predictable processors than multi-core systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core to external memories or peripherals communications must be established. Several NoCs targeting hard real-time systems, made of specific hardware extensions, have been designed. However, none of these extensions are currently available in commercially existing NoC-based many-core architectures, that instead rely on wormhole switching with round-robin arbitration. In this paper, we thus demonstrate three properties of such NoC-based wormhole networks to identify worst-case scenarios and reduce the pessimism when modeling flows in contentions. We then describe and evaluate an algorithm to compute Worst-Case Traversal Time (WCTT) of flows that uses these properties. In particular, our results show that the pessimism can be reduced up to 50% compared to current state-of-the-art real-time packet schedulability analysis.
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-01836859
Contributor : Léna Le Roy <>
Submitted on : Thursday, July 12, 2018 - 3:05:26 PM
Last modification on : Thursday, June 27, 2019 - 4:27:53 PM

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L. Abdallah, M. Jan, J. Ermont, C. Fraboul. Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores. 10th IEEE International Symposium on Industrial Embedded Systems (SIES), Jun 2015, Siegen, Germany. pp.59-68, ⟨10.1109/SIES.2015.7185041⟩. ⟨cea-01836859⟩

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