Fine-grain analysis of the parameters involved in aging of digital circuits

B. Ouattara (1) , O. Heron (1) , C. Sandionigi (1)

1 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST

Integrated circuits' aging is recognized as a key reliability bottleneck. Its estimation at design time is mandatory to define the lifetime of the circuit and its monitoring during the circuit's operation is necessary to guarantee high performances and avoid timing failures. Various parameters are involved in the process of aging. The knowledge of their impact can help the designer in optimizing the estimation at design time or selecting which parameters are most critical to monitor. This paper presents a fine-grain analysis of the parameters involved in the degradation of digital circuits.

Mots clés: Digital circuits; Systems analysis; Timing circuits; Design time; Fine-grain analysis; Timing failures; Electric network analysis

Domaines: Sciences de l'ingénieur [physics]

B. Ouattara, O. Heron, C. Sandionigi. Fine-grain analysis of the parameters involved in aging of digital circuits. 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2016, Sant Feliu de Guixols, Spain. pp.51-53, ⟨10.1109/IOLTS.2016.7604671⟩. ⟨cea-01836856⟩