Resistive memories for spike-based neuromorphic circuits

Abstract : In the last decade machine learning algorithms have proven unprecedented performance to solve many real-world detection and classification tasks, for example in image or speech recognition. Despite these advances, there are still some deficits. First, these algorithms require significant memory access thus ruling out an implementation using standard platforms (e.g. GPUs, FPGAS) for embedded applications. Second, most machine leaning algorithms need to be trained with huge data sets (supervised learning). Resistive memories (RRAM) have demonstrated to be a promising candidate to overcome both these constrains. RRAM arrays can act as a dot product accelerator, which is one of the main building blocks in neuromorphic computing systems. This approach could provide improvements in power and speed with respect to the GPU-based networks. Moreover RRAM devices are promising candidates to emulate synaptic plasticity, the capability of synapses to enhance or diminish their connectivity between neurons, which is widely believed to be the basis for learning and memory in the brain. Neural systems exhibit various types and time periods of plasticity, e.g. synaptic modifications can last anywhere from seconds to days or months. In this work we proposed an architecture that implements both Short-And Long-Term Plasticity rules (STP and LTP) using RRAM arrays. We showed the benefits of utilizing both kinds of plasticity with two different applications, visual pattern extraction and decoding of neural signals. LTP allows the neural networks to learn patterns without training data set (unsupervised learning), and STP makes the learning process very robust against environmental noise.
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-01836851
Contributor : Léna Le Roy <>
Submitted on : Thursday, July 12, 2018 - 3:05:10 PM
Last modification on : Tuesday, February 26, 2019 - 8:22:06 AM

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E. Vianello, T. Werner, O. Bichler, A. Valentian, G. Molas, et al.. Resistive memories for spike-based neuromorphic circuits. 2017 IEEE International Memory Workshop (IMW), May 2017, Monterey,, United States. ⟨10.1109/IMW.2017.7939100⟩. ⟨cea-01836851⟩

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