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Journal Articles Procedia Computer Science Year : 2016

Pattern based cache coherency architecture for embedded manycores

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Abstract

Modern parallel programming frameworks like OpenMP often rely on shared memory concepts to harness the processing power of parallel systems. But for embedded devices, memory coherence protocols tend to account for a sizable portion of chip's power consumption. This is why any means to lower this impact is important. Our idea for this issue is to use the fact that most of usual workloads display a regular behavior with regards to their memory accesses to prefetch the relevant memory lines in locale caches of execution cores on a manycore system. Our contributions are, on one hand the specifications of a hardware IP for prefetching memory access patterns, and on another hand, a hybrid protocol which extends the classic MESI/baseline architecture to reduce the control and coherence related traffic by at least an order of magnitude. Evaluations are done on several benchmark programs and show the potential of this approach.
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Dates and versions

cea-01831555 , version 1 (06-07-2018)

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Attribution - NonCommercial - NoDerivatives - CC BY 4.0

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J. Marandola, S. Louise, L. Cudennec. Pattern based cache coherency architecture for embedded manycores. Procedia Computer Science, 2016, 80, pp.1542-1553. ⟨10.1016/j.procs.2016.05.481⟩. ⟨cea-01831555⟩
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