Pattern based cache coherency architecture for embedded manycores
Abstract
Modern parallel programming frameworks like OpenMP often rely on shared memory concepts to harness the processing power of parallel systems. But for embedded devices, memory coherence protocols tend to account for a sizable portion of chip's power consumption. This is why any means to lower this impact is important. Our idea for this issue is to use the fact that most of usual workloads display a regular behavior with regards to their memory accesses to prefetch the relevant memory lines in locale caches of execution cores on a manycore system. Our contributions are, on one hand the specifications of a hardware IP for prefetching memory access patterns, and on another hand, a hybrid protocol which extends the classic MESI/baseline architecture to reduce the control and coherence related traffic by at least an order of magnitude. Evaluations are done on several benchmark programs and show the potential of this approach.
Keywords
Application programming interfaces (API)
Internet protocols
Memory architecture
Multiprocessing systems
Network architecture
Parallel processing systems
Parallel programming
Benchmark programs
Cache coherence protocols
Chip multi-processors
Manycore systems
Memory access patterns
Memory coherence protocols
Processing power
Programming framework
Cache memory
Chip Multi-Processor
Cache Coherence Protocol
Memory Access Patterns
Domains
Computer Science [cs]
Origin : Publisher files allowed on an open archive
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