Pattern based cache coherency architecture for embedded manycores

J. Marandola (1) , S. Louise (1) , L. Cudennec (1)

1 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST

Modern parallel programming frameworks like OpenMP often rely on shared memory concepts to harness the processing power of parallel systems. But for embedded devices, memory coherence protocols tend to account for a sizable portion of chip's power consumption. This is why any means to lower this impact is important. Our idea for this issue is to use the fact that most of usual workloads display a regular behavior with regards to their memory accesses to prefetch the relevant memory lines in locale caches of execution cores on a manycore system. Our contributions are, on one hand the specifications of a hardware IP for prefetching memory access patterns, and on another hand, a hybrid protocol which extends the classic MESI/baseline architecture to reduce the control and coherence related traffic by at least an order of magnitude. Evaluations are done on several benchmark programs and show the potential of this approach.

Mots clés: Application programming interfaces (API); Internet protocols; Memory architecture; Multiprocessing systems; Network architecture; Parallel processing systems; Parallel programming; Benchmark programs; Cache coherence protocols; Chip multi-processors; Manycore systems; Memory access patterns; Memory coherence protocols; Processing power; Programming framework; Cache memory; Chip Multi-Processor; Cache Coherence Protocol; Memory Access Patterns

Domaines: Informatique [cs]

J. Marandola, S. Louise, L. Cudennec. Pattern based cache coherency architecture for embedded manycores. Procedia Computer Science, 2016, 80, pp.1542-1553. ⟨10.1016/j.procs.2016.05.481⟩. ⟨cea-01831555⟩