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Journal Articles ACM Transactions on Embedded Computing Systems (TECS) Year : 2014

HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

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Abstract

The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, cluster-based many-core accelerators with a shared hierarchical memory have emerged. Handling synchronizations on these architectures is critical since parallel implementations speed-ups of embedded applications strongly depend on the ability to exploit the largest possible number of cores while limiting task management overhead. This article presents the combination of a low-overhead complete runtime software and a flexible hardware accelerator for synchronizations called HARS (Hardware-Assisted Runtime Software). Experiments on a multicore test chip showed that the hardware accelerator for synchronizations has less than 1% area overhead compared to a cluster of the chip while reducing synchronization latencies (up to 2.8 times compared to a test-and-set implementation) and contentions. The runtime software part offers basic features like memory management but also optimized execution engines to allow the easy and efficient extraction of the parallelism in applications with multiple programming models. By using the hardware acceleration as well as a very low overhead task scheduling software technique, we show that HARS outperforms an optimized state-of-the-art task scheduler by 13% for the execution of a parallel application.
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Dates and versions

cea-01818892 , version 1 (19-06-2018)

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Cite

Y. Lhuillier, M. Ojail, A. Guerre, J.-M. Philippe, K.B. Chehida, et al.. HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures. ACM Transactions on Embedded Computing Systems (TECS), 2014, 13 (3s), ⟨10.1145/2517311⟩. ⟨cea-01818892⟩

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