Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations

N. Ventroux (1) , J. Peeters (1) , T. Sassolas (1) , J.C. Hoe (2)

1 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST
2 CALCM - Computer Architecture Laboratory

The complexity of SystemC virtual prototyping is continuously increasing. Accelerating RTL/TLM SystemC simulations is essential to control future SoC development cost and time-to-market. In this paper, we present RAVES, a highly-parallel special-purpose multicore architecture that achieves simulation performance more efficiently by parallel execution of light-weight user-level threads on many small cores. We present a design study based on the virtual prototype of RAVES processors running a co-designed custom SystemC kernel. Our evaluation suggests that a 64-core RAVES processor can deliver up to 4.47× more simulation performance than a high-end x86 processor.

Mots clés: Computer simulation; Embedded systems; Logic design; Parallel processing systems; Software architecture; Development costs; Multicore architectures; Parallel executions; Simulation performance; Time-to-market; User-level threads; Virtual prototype; Virtual prototyping; System-on-chip

Domaines: Sciences de l'ingénieur [physics]

N. Ventroux, J. Peeters, T. Sassolas, J.C. Hoe. Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Jul 2014, Agios Konstantinos, Greece. pp.250-257, ⟨10.1109/SAMOS.2014.6893218⟩. ⟨cea-01817866⟩