Memory Reliability Improvement Based on Maximized Error-Correcting Codes

Abstract : Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable.
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https://hal-cea.archives-ouvertes.fr/cea-01777396
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Submitted on : Tuesday, April 24, 2018 - 4:38:52 PM
Last modification on : Thursday, February 7, 2019 - 3:43:59 PM

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Valentin Gherman, Samuel Evain, Yannick Bonhomme. Memory Reliability Improvement Based on Maximized Error-Correcting Codes. Journal of Electronic Testing, Springer Verlag, 2013, 29, pp.601 - 608. ⟨10.1007/s10836-013-5396-6⟩. ⟨cea-01777396⟩

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