S. Abbaspour and F. Brandner, Alignment of memory transfers of a time-predictable stack cache, Proceedings of the junior researcher workshop on real-time computing, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01108105

S. Abbaspour, F. Brandner, and M. Schoeberl, A time-predictable stack cache, Proceedings of the workshop on software technologies for embedded and ubiquitous systems, 2013.
DOI : 10.1109/isorc.2013.6913225
URL : https://hal.archives-ouvertes.fr/hal-01108105

S. Abbaspour, A. Jordan, and F. Brandner, Lazy spilling for a time-predictable stack cache: Implementation and analysis, Proceedings of the workshop on worst-case execution time analysis, vol.39, pp.83-92, 2014.
DOI : 10.1109/isorc.2013.6913225
URL : https://hal.archives-ouvertes.fr/hal-01056216

S. Abbaspour, F. Brandner, A. Naji, and J. M. , Efficient context switching for the stack cache: implementation and analysis, Proceedings of the international conference on real time and networks systems, vol.15, pp.119-128, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01246348

A. V. Aho, M. S. Lam, R. Sethi, and J. D. Ullman, Compilers: principles, techniques, and tools, 2006.

S. Altmeyer and C. Burguiere, A new notion of useful cache block to improve the bounds of cache-related preemption delay, Euromicro conference on real-time systems, vol.09, pp.109-118, 2009.

S. Altmeyer, R. Davis, and C. Maiza, Improved cache related pre-emption delay aware response time analysis for fixed priority pre emptive systems, Real-Time Syst, vol.48, issue.5, pp.499-526, 2012.
DOI : 10.1007/s11241-012-9152-2

S. Baruah, The limited-preemption uniprocessor scheduling of sporadic task systems, In: 17th euromicro conference on real-time systems (ECRTS'05), pp.137-144, 2005.

, Advances in real-time systems. In: preemptive priority-based scheduling: an appropriate engineering approach, Burns A, pp.225-248, 1995.

D. Chabrol, D. Roux, V. David, J. M. Hmid, M. A. Oudin et al., Time-and angle-triggered real-time kernel, Design, automation and test in, vol.13, pp.1060-1062, 2013.
DOI : 10.7873/date.2013.223
URL : https://hal.archives-ouvertes.fr/cea-01844717

T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. Stein, M. R. Guthaus et al., MiBench: a free, commercially representative embedded benchmark suite, Proceedings of the workshop on workload characterization, p.1, 2001.

M. S. Hecht and J. D. Ullman, Analysis of a simple algorithm for global data flow problems, Symposium on principles of programming languages (POPL'73, pp.207-217, 1973.

M. Jan, V. David, J. Lalande, and M. Pitel, Usage of the safety-oriented real-time oasis approach to build deterministic protection relays, Symposium on industrial embedded systems, SIES'10, pp.128-135, 2010.

A. Jordan, F. Brandner, and M. Schoeberl, Static analysis of worst-case stack cache behavior, Proceedings of the conference on real-time networks and systems, RTNS'13, pp.55-64, 2013.
DOI : 10.1145/2516821.2516828

J. B. Kam and J. D. Ullman, Global data flow analysis and iterative algorithms, J ACM, vol.23, issue.1, pp.158-171, 1976.
DOI : 10.1145/321921.321938

C. G. Lee, J. Hahn, Y. M. Seo, S. L. Min, R. Ha et al., Analysis of cache-related preemption delay in fixed-priority preemptive scheduling, IEEE Trans Comput, vol.47, issue.6, pp.700-713, 1998.

Y. Li and S. Malik, Performance analysis of embedded software using implicit path enumeration, Proceedings of the design automation conference, ACM, DAC '95, pp.456-461, 1995.

S. Metzlaff, I. Guliashvili, S. Uhrig, and T. Ungerer, A dynamic instruction scratchpad memory for embedded processors managed by hardware, Proceedings of the architecture of computing systems conference, pp.122-134, 2011.

J. Mische, S. Uhrig, F. Kluge, and T. Ungerer, Using smt to hide context switch times of large realtime tasksets, Proceedings of conference on embedded and real-time computing systems and applications, RTCSA'10, pp.255-264, 2010.

L. E. Olson, Y. Eckert, S. Manne, and M. D. Hill, Revisiting stack caches for energy efficiency, 2014.

J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, PRET DRAM controller: bank privatization for predictability and temporal isolation, Proceedings of the conference on hardware/software codesign and system synthesis, pp.99-108, 2011.

C. Rochange, S. Uhrig, P. Sainrat, L. Wiley, M. Schoeberl et al., Towards a time-predictable dual-issue microprocessor: the patmos approach, Proceedings of bringing theory to practice: predictability and performance in embedded systems, vol.18, pp.11-21, 2011.

V. Soundararajan and A. Agarwal, Dribbling registers: a mechanism for reducing context switch latency in large-scale multiprocessors, 1992.

M. Thorup, Integer priority queues with decrease key in constant time and the single source shortest paths problem, J Comput Syst Sci, vol.69, issue.3, pp.330-353, 2004.
DOI : 10.1145/780542.780566

E. Tune, R. Kumar, D. M. Tullsen, and B. Calder, Balanced multithreading: Increasing throughput via a low cost multithreading hierarchy, Proceedings of the symposium on microarchitecture, MICRO'04, pp.183-194, 2004.
DOI : 10.1109/micro.2004.8
URL : http://www.microarch.org/micro37/papers/17_Tune-BalancedMultithreading.pdf

Y. Wang and M. Saksena, Scheduling fixed-priority tasks with preemption threshold, Real-time computing systems and applications, 1999. RTCSA '99. sixth international conference on, pp.328-335, 1999.

R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister et al., Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems, Trans Comput-Aided Des Integr Circ Syst, vol.28, issue.7, pp.966-978, 2009.
DOI : 10.1109/tcad.2009.2013287