Skip to Main content Skip to Navigation
Conference papers

Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces

Abstract : —This paper presents the computing model for In-Memory Computing architecture based on SRAM memory that embeds computing abilities. This memory concept offers significant performance gains in terms of energy consumption and execution time. To handle the interaction between the memory and the CPU, new memory instruction codes were designed. These instructions are communicated by the CPU to the memory, using standard SRAM buses. This implementation allows (1) to embed In-Memory Computing capabilities on a system without Instruction Set Architecture (ISA) modification, and (2) to finely interlace CPU instructions and in-memory computing instructions.
Document type :
Conference papers
Complete list of metadatas

Cited literature [13 references]  Display  Hide  Download

https://hal-cea.archives-ouvertes.fr/cea-01757656
Contributor : Henri-Pierre Charles <>
Submitted on : Tuesday, April 3, 2018 - 6:43:01 PM
Last modification on : Thursday, June 11, 2020 - 5:04:07 PM

File

main.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : cea-01757656, version 1

Collections

Relations

  • is illustrated by cea-01757665 - Transparents de la présentation

Citation

Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel. Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces. Design, Automation and Test in Europe, Mar 2018, Dresde, Germany. ⟨cea-01757656⟩

Share

Metrics

Record views

638

Files downloads

1181