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Workload-dependent BTI analysis in a processor core at high level

C.A Sandionigi 1 E.A Piriou 1 S.A Mbarek 1 V.B Huard 2 O. Heron 1
1 LIST - Laboratoire d'Intégration des Systèmes et des Technologies
2 ST-CROLLES - STMicroelectronics [Crolles]
Abstract : This work presents a software tool that enables joint architecture simulation and estimation of ageing-induced timing drifts at register-transfer level (RTL). The objective is to enable design exploration of processor microarchitecture under ageing constraint. The tool makes the bridge between user application, micro-architecture design, PVT corner and device-level degradation model. The environment will aid design engineers to apply early software and architecture optimizations at RTL for a better power consumption, performance and failure rate tradeoff. © 2015 IEEE.
Keywords : Architecture optimization Bridges Computer architecture Computer software Integrated circuit design Integrated circuits Micro-architecture design Micro architectures NBTI Program processors Reduced instruction set computing Register transfer level RISC processors RTL Simulation
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https://hal-cea.archives-ouvertes.fr/cea-01719961
Contributor : Bruno Savelli <>
Submitted on : Wednesday, February 28, 2018 - 4:31:44 PM
Last modification on : Monday, February 10, 2020 - 6:12:35 PM

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C.A Sandionigi, E.A Piriou, S.A Mbarek, V.B Huard, O. Heron. Workload-dependent BTI analysis in a processor core at high level. IEEE International Reliability Physics Symposium Proceedings, Apr 2015, Monterrey, United States. pp.CA61--CA66, ⟨10.1109/IRPS.2015.7112784⟩. ⟨cea-01719961⟩

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