Workload-dependent BTI analysis in a processor core at high level

C.A Sandionigi (1) , E.A Piriou (1) , S.A Mbarek (1) , V.B Huard (2) , O. Heron (1)

1 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
2 ST-CROLLES - STMicroelectronics [Crolles]

This work presents a software tool that enables joint architecture simulation and estimation of ageing-induced timing drifts at register-transfer level (RTL). The objective is to enable design exploration of processor microarchitecture under ageing constraint. The tool makes the bridge between user application, micro-architecture design, PVT corner and device-level degradation model. The environment will aid design engineers to apply early software and architecture optimizations at RTL for a better power consumption, performance and failure rate tradeoff. © 2015 IEEE.

Keywords: Architecture optimization; Bridges; Computer architecture; Computer software; Integrated circuit design; Integrated circuits; Micro-architecture design; Micro architectures; NBTI; Program processors; Reduced instruction set computing; Register transfer level; RISC processors; RTL; Simulation

Domains: Physics [physics]

C.A Sandionigi, E.A Piriou, S.A Mbarek, V.B Huard, O. Heron. Workload-dependent BTI analysis in a processor core at high level. IEEE International Reliability Physics Symposium Proceedings, Apr 2015, Monterrey, United States. pp.CA61--CA66, ⟨10.1109/IRPS.2015.7112784⟩. ⟨cea-01719961⟩