Advanced characterizations of fluorine-free tungsten film and its application as low resistance liner for PCRAM

Abstract : Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step. The W liner with thicknesses ranging from 3 to 4 nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.
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Materials Science in Semiconductor Processing, Elsevier, 2017, 71, pp.433 - 440. 〈10.1016/j.mssp.2017.08.033〉
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Philippe Rodriguez, Romain Famulok, Yannick Le Friec, Jean-Philippe Reynard, Benoit-Noël Bozon, et al.. Advanced characterizations of fluorine-free tungsten film and its application as low resistance liner for PCRAM. Materials Science in Semiconductor Processing, Elsevier, 2017, 71, pp.433 - 440. 〈10.1016/j.mssp.2017.08.033〉. 〈cea-01586412〉

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