Towards on-line estimation of BTI/HCI-induced frequency degradation

Abstract : This work proposes a new bottom-up approach for on-line estimation of circuit performance loss due to BTI/HCI effects. Built on the top of device-level models, it takes into account all factors that impact global circuit aging, namely, process, topology, workload, voltage and temperature variations. The proposed model is fed by voltage and temperature monitors that on-line track dynamic variations. This allows an accurate assessment of the evolution of the circuit critical path delays during its operation. Its accuracy is evaluated here on two circuits implemented in 28nm FD-SOI technology.
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Communication dans un congrès
IEEE International Reliability Physics Symposium, Apr 2017, Monterey, United States. 2017, 〈10.1109/IRPS.2017.7936355〉
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https://hal-cea.archives-ouvertes.fr/cea-01571643
Contributeur : Suzanne Lesecq <>
Soumis le : jeudi 3 août 2017 - 11:12:49
Dernière modification le : jeudi 15 mars 2018 - 15:06:06

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IRPS_17f_v02.pdf
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Mauricio Altieri, Suzanne Lesecq, Edith Beigne, Olivier Héron. Towards on-line estimation of BTI/HCI-induced frequency degradation. IEEE International Reliability Physics Symposium, Apr 2017, Monterey, United States. 2017, 〈10.1109/IRPS.2017.7936355〉. 〈cea-01571643〉

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