Semi-parallel reconfigurable architectures for real-time LDPC decoding, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004., pp.579-585, 2004. ,
DOI : 10.1109/ITCC.2004.1286526
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.59.1685
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, issue.1, pp.98-111, 2011. ,
DOI : 10.1109/TCSI.2010.2055250
Resource efficient LDPC decoders for multimedia communication, Integration, the VLSI Journal, vol.48, pp.213-220, 2015. ,
DOI : 10.1016/j.vlsi.2014.09.002
URL : http://arxiv.org/pdf/1305.6216
High-throughput layered decoder implementation for quasi-cyclic LDPC codes, IEEE Journal on Selected Areas in Communications, vol.27, issue.6, pp.985-994, 2009. ,
DOI : 10.1109/JSAC.2009.090816
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.454.6697
A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS, IEEE Asian Solid-State Circuits Conference 2011, pp.317-320, 2011. ,
DOI : 10.1109/ASSCC.2011.6123576
84 mm 2 847?955 Mb/s 397 mW dual-path fully-overlapped QC-LDPC decoder for the WiMAX system in 0.13 µm CMOS, IEEE Symp. on VLSI Circuits (VLSIC), pp.211-212, 2010. ,
Non-surjective finite alphabet iterative decoders, 2016 IEEE International Conference on Communications (ICC), pp.1-6, 2016. ,
DOI : 10.1109/ICC.2016.7511111
URL : https://hal.archives-ouvertes.fr/cea-01567164
Code-aware quantizer design for finite-precision min-sum decoders, 2016 IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom), 2016. ,
DOI : 10.1109/BlackSeaCom.2016.7901540
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, issue.4, pp.483-488, 2007. ,
DOI : 10.1109/TED.2007.895247
Algorithms of finding the first two minimum values and their hardware implementation, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, issue.11, pp.3430-3437, 2008. ,