Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

Abstract : —In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. The proposed architecture provides full design time flexibility, i.e., it can accommodate any Quasi-Cyclic (QC) LDPC code, and also allows redefining a number of parameters of the QC-LDPC code at the run time. The main novelty of the paper consists of: (1) a new low-cost processing unit that merges in an efficient way the logical functionalities of the Variable-Node Unit (VNU) and the A Posteriori Log-Likelihood Ratio (AP-LLR) unit, (2) a high speed, low-cost Check-Node Unit (CNU) architecture, which is executed twice in order to complete the computation of the check-node messages at each iteration, (3) a splitting of the iteration processing in two perfectly symmetric stages, executed in two consecutive clock cycles, each one using exactly the same processing resources; the processing load is perfectly balanced between the two clock cycles, thus yielding an optimal clock frequency. Synthesis results targeting a 65nm CMOS technology for a (3, 6)-regular (648, 1296) Quasi-Cyclic LDPC code and for the WiMax (1152, 2304) irregular QC-LDPC code show significant improvements in terms of area and throughput compared to the baseline architecture discussed in this paper, as well as several state of the art implementations.
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Communication dans un congrès
2016 Euromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. 2016, IEEE Conference Publication. 〈http://ieeexplore.ieee.org/document/7723558/?reload=true〉. 〈10.1109/DSD.2016.33〉
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https://hal-cea.archives-ouvertes.fr/cea-01566283
Contributeur : Sylvie Mayrargue <>
Soumis le : jeudi 20 juillet 2017 - 18:45:13
Dernière modification le : jeudi 3 mai 2018 - 15:18:05

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Thien T. Nguyen-Ly, Tushar Gupta, Manuel Pezzin, Valentin Savin, David Declercq, et al.. Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units. 2016 Euromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. 2016, IEEE Conference Publication. 〈http://ieeexplore.ieee.org/document/7723558/?reload=true〉. 〈10.1109/DSD.2016.33〉. 〈cea-01566283〉

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