. A. Wm, S. A. Wulf, and . Mckee, Hitting the memory wall: implications of the obvious, ACM SIGARCH Comp. Arch. News, vol.23, issue.1, pp.20-24, 1995.

M. V. Wilkes, The memory wall and the CMOS end-point, ACM SIGARCH Computer Architecture News, vol.23, issue.4, pp.4-6, 1995.
DOI : 10.1145/218864.218865

S. Hsiao, Design of low-leakage multi-port SRAM for register file in graphics processing unit, 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014.
DOI : 10.1109/ISCAS.2014.6865601

G. Burda, A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file, 2010 IEEE International Solid-State Circuits Conference, (ISSCC), pp.286-287, 2010.
DOI : 10.1109/ISSCC.2010.5433924

M. Horowitz, 1.1 Computing's energy problem (and what we can do about it), 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.10-14, 2014.
DOI : 10.1109/ISSCC.2014.6757323
URL : https://hal.archives-ouvertes.fr/insu-01488608

M. Gokhale, Processing in memory: the Terasys massively parallel PIM array, Computer, vol.28, issue.4, pp.23-31, 1995.
DOI : 10.1109/2.375174

. Zhu, A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing, 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013.
DOI : 10.1109/3DIC.2013.6702348

P. Jain, Intelligent SRAM (ISRAM) for Improved Embedded System Performance, proceedings of DAC, 2003.

S. Hamdioui, Memristor based computation-in-memory architecture for data-intesive applications, DATE, pp.1718-1725, 2015.

P. Dlugosch, An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing, IEEE Transactions on Parallel and Distributed Systems, vol.25, issue.12, pp.3088-3098, 2014.
DOI : 10.1109/TPDS.2014.8

. Mai, Video-Active RAM: A Processor-in-Memory Architecture for Video Coding Applications, ISCA, pp.161-171, 2010.

. Jeloka, A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory, JSSC, vol.51, issue.99, pp.1009-121, 2016.

. Shibata, A 0.5V 25MHz 1mW 256kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment-sure write operation by using step-down negatively overdriven bit-line scheme, JSSC, vol.41, issue.3, pp.728-742, 2006.
URL : https://hal.archives-ouvertes.fr/in2p3-01152574

. Mukhopadhyay, Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.12, pp.1859-18880, 2005.
DOI : 10.1109/TCAD.2005.852295

W. D. Hillis, The Connectino Machine, 1989.

L. Guy, . Steele, and . Jr, Connection Machine Lisp: Fine-grained Parallel Symbolic Processing, Proceedings of the 1986 ACM Conf. on LISP and Functional Programming, pp.279-277

A. Elfes, Occupancy grids: a stochastic representation for active robot perception, Sixth Conference on Uncertainity in AI, 1990.

T. Rakotovao, Multi-sensor fusion of occupancy grids based on integer arithmetic, 2016 IEEE International Conference on Robotics and Automation (ICRA), 2016.
DOI : 10.1109/ICRA.2016.7487330
URL : https://hal.archives-ouvertes.fr/cea-01273335

C. Coué, Bayesian Occupancy Filtering for Multitarget Tracking: An Automotive Application, The International Journal of Robotics Research, vol.99, issue.1, pp.19-30, 2006.
DOI : 10.1177/0278364906061158