I. M. Panades, A Fine-Grain Variation-Aware Dynamic <formula formulatype="inline"><tex Notation="TeX">${\rm Vdd}$</tex></formula>-Hopping AVFS Architecture on a 32 nm GALS MPSoC, IEEE Journal of Solid-State Circuits, vol.49, issue.7, pp.1475-1486, 2014.
DOI : 10.1109/JSSC.2014.2317137

D. Melpignano, Platform 2012, a many-core computing accelerator for embedded SoCs, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.1137-1142, 2012.
DOI : 10.1145/2228360.2228568

A. Varghese, Programming the adapteva epiphany 64-core network-on-chip coprocessor, IPDPS, pp.984-992, 2014.

F. Conti, Energy-efficient vision on the pulp platform for ultralow power parallel computing, IEEE SiPS: Design and Implem, 2014.

S. Zhuravlev, Survey of Energy-Cognizant Scheduling Techniques, IEEE Transactions on Parallel and Distributed Systems, vol.24, issue.7, pp.1447-1464, 2013.
DOI : 10.1109/TPDS.2012.20

Q. Wu, Formal online methods for voltage/frequency control in multiple clock domain microprocessors Design and management of voltage-frequency island partitioned networks-on-chip, ASPLOS IEEE Trans. VLSI, vol.32, issue.17, pp.248-259, 2004.

S. Garg, D. Marculescu, and R. Marculescu, Custom feedback control, Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, ISLPED '10, pp.425-430, 2010.
DOI : 10.1145/1840845.1840939

P. Bogdan, R. Marculescu, and S. Jain, Dynamic power management for multidomain system-on-chip platforms, ACM Transactions on Design Automation of Electronic Systems, vol.18, issue.4, 2013.
DOI : 10.1145/2504904

P. Juang, Coordinated, distributed, formal energy management of chip multiprocessors, Proceedings of the 2005 international symposium on Low power electronics and design , ISLPED '05, 2005.
DOI : 10.1145/1077603.1077637

A. Alimonda, A Feedback-Based Approach to DVFS in Data-Flow Applications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.11, 2009.
DOI : 10.1109/TCAD.2009.2030439

G. Almeida, PI and PID regulation approaches for performanceconstrained adaptive multiprocessor system-on-chip Embedded Systems Letters, pp.77-80, 2011.

S. Carta, A control theoretic approach to energy-efficient pipelined computation in MPSoCs, ACM Transactions on Embedded Computing Systems, vol.6, issue.4, 2007.
DOI : 10.1145/1274858.1274865

R. David, P. Bogdan, and R. Marculescu, Dynamic power management for multicores: Case study using the intel SCC, VLSI-SoC, 2012.

R. Z. Ayoub, OS-level power minimization under tight performance constraints in general purpose systems, IEEE/ACM International Symposium on Low Power Electronics and Design, 2011.
DOI : 10.1109/ISLPED.2011.5993657

M. Altieri, Coupled voltage and frequency control for DVFS management, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013.
DOI : 10.1109/PATMOS.2013.6662175

T. Serre, L. Wolf, and T. Poggio, Object Recognition with Features Inspired by Visual Cortex, 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05), pp.994-1000, 2005.
DOI : 10.1109/CVPR.2005.254

M. Riesenhuber and T. Poggio, Hierarchical models of object recognition in cortex, Nature Neuroscience, vol.3, issue.Supp, pp.1199-1204, 1999.
DOI : 10.1038/81479

Z. Lu, Control-theoretic dynamic frequency and voltage scaling for multimedia workloads, Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems , CASES '02, pp.156-163, 2002.
DOI : 10.1145/581630.581654