C. Ebert and C. Jones, Embedded Software: Facts, Figures, and Future, Computer, vol.42, issue.4, 2009.
DOI : 10.1109/MC.2009.118

D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva et al., Poweraware microarchitecture: design and modeling challenges for nextgeneration microprocessors, 2000.

M. Pedram, Power optimization and management in embedded systems, ASP-DAC, 2001.

K. Yu, D. Han, C. Youn, S. Hwang, and J. Lee, Power-aware task scheduling for big.LITTLE mobile processor, 2013 International SoC Design Conference (ISOCC), 2013.
DOI : 10.1109/ISOCC.2013.6864009

S. Reda and A. N. Nowroz, Power Modeling and Characterization of Computing Devices: A Survey, Foundations and Trends?? in Electronic Design Automation, vol.6, issue.2, 2012.
DOI : 10.1561/1000000022

M. Sichitiu, Cross-layer scheduling for power efficiency in wireless sensor networks, IEEE INFOCOM 2004, 2004.
DOI : 10.1109/INFCOM.2004.1354585

A. Bogliolo and L. Benini, Node sampling, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design , ICCAD '98, 1998.
DOI : 10.1145/288548.289071

V. Tiwari, S. Malik, A. Wolfe, and M. T. Chien-lee, Instruction level power analysis and optimization of software, Journal of VLSI Signal Processing, 1996.

J. Laurent, N. Julien, E. Senn, and E. Martin, Functional level power analysis: an efficient approach for modeling the power consumption of complex processors, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1268921
URL : https://hal.archives-ouvertes.fr/hal-00013979

H. Blume, D. Becker, L. Rotenberg, M. Botteck, J. Brakensiek et al., Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures, Journal of Systems Architecture, vol.53, issue.10, 2007.
DOI : 10.1016/j.sysarc.2007.01.002

D. Kim, J. Kim, and J. Hong, A Power Consumption Analysis Technique Using UML-Based Design Models in Embedded Software Development, SOFSEM'11, 2011.
DOI : 10.1109/30.234637

T. Arpinen, E. Salminen, T. D. Hmlinen, and M. Hnnikinen, MARTE profile extension for modeling dynamic power management of embedded systems, Journal of Systems Architecture, vol.58, issue.5, 2012.
DOI : 10.1016/j.sysarc.2011.01.003

C. Gomez, J. Deantoni, and F. Mallet, Multi-view Power Modeling Based on UML, MARTE and SysML, 2012 38th Euromicro Conference on Software Engineering and Advanced Applications, 2012.
DOI : 10.1109/SEAA.2012.66
URL : https://hal.archives-ouvertes.fr/hal-00688853

. Standard and . Ip-xact, Standard Structure for Packaging, Integrating , and Reusing IP within Tools Flows, IEEE Std, 1685.

L. Scheffer, L. Lavagno, and G. Martin, EDA for IC System Design, Verification, and Testing (Electronic Design Automation for Integrated Circuits Handbook), 2006.

D. Melpignano, Platform 2012, a many-core computing accelerator for embedded SoCs, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, 2012.
DOI : 10.1145/2228360.2228568

T. Ducroux, G. Haugou, V. Risson, and P. Vivet, Fast and accurate power annotated simulation: Application to a many-core architecture, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013.
DOI : 10.1109/PATMOS.2013.6662173