eISP: a Programmable Processing Architecture for Smart Phone Image Enhancement

Thevenin Mathieu (1) , Letellier Laurent (1) , Paindavoine Michel (2) , Schmit Renaud (1) , Heyrman Barthelemy (2)

1 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
2 Le2i - Laboratoire Electronique, Informatique et Image [UMR6306]

Today's smart phones, with their embedded high-resolution video sensors, require computing capacities that are too high to easily meet stringent silicon area and power consumption requirements (some one and a half square millimeters and half a watt) especially when programmable components are used. To develop such capacities, integrators still rely on dedicated low resolution video processing components, whose drawback is low flexibility. With this in mind, our paper presents eISP {--} a new, fully programmable Embedded Image Signal Processor architecture, now validated in {TSMC 65nm} technology to achieve a capacity of {16.8 GOPs} at {233 MHz}, for {1.5 mm$^2$} of silicon area and a power consumption of {250 mW}. Its resulting efficiency ({67 MOPs/mW}), has made eISP the leading programmable architecture for signal processing, especially for {HD 1080p} video processing on embedded devices such as smart phone.

Mots clés: eISP; image processing; video pipe; CMOS; sensor; low power; small silicon; SIMD; Multi-SIMD; computing tile; demosaïcking; demosaicing; TSMC 65nm; milliwatt; mm²

Domaines: Traitement du signal et de l'image [eess.SP]; Traitement du signal et de l'image [eess.SP]

Thevenin Mathieu, Letellier Laurent, Paindavoine Michel, Schmit Renaud, Heyrman Barthelemy. eISP: a Programmable Processing Architecture for Smart Phone Image Enhancement. 2009. ⟨cea-00445710⟩